This invention relates to the fabrication of integrated circuits; and more particularly, it relates to circuits for measuring the amount of misalignment between the various patterned layers in the integrated circuit.
As is well known, the fabrication of an integrated circuit includes the steps of patterning several different layers on a semiconductor substrate. Typically, a diffused or implanted region is first patterned in the substrate; thereafter a polysilicon layer is patterned over the diffused or implanted region; and subsequently at least one metal layer is patterned over the polysilicon. Also typically, these patterned conductive layers are separated by patterned insulating layers.
In the fabrication process, a different mask is used to pattern each layer. For example, to pattern the polysilicon layer, an unpatterned layer of polysilicon is first deposited across the substrate; then an unpatterned layer of photoresist is deposited over the layer of polysilicon; then a mask is used to expose selected areas of the resist to ultraviolet light; then the exposed areas are removed by a chemical or plasma etch; and then the regions of the polysilicon layer which are not covered by the remaining resist are removed by another etch.
Also in the fabrication of an integrated circuit, only a certain amount of misalignment between the masks that define the various conductor layers can be tolerated. Typically, that amount might be .+-.1 micron; but the amount of misalignment that is allowable decreases as the dimensions of the circuit features decrease. Thus, in order to monitor whether or not the circuit that is being fabricated is within tolerance, it is very desirable to provide a way to measure the amount of misalignment that occurs between the masks that define the conductive layers in the circuit.
Presently, this misalignment is measured via the optical inspection by an operator of an alignment pattern that is put on the substrate. For example, a portion of one of the conductive layer may be patterned as a large square, while a portion of another conductive layer is patterned as a small square which nominally is at the center of the large square. After the two squares are fabricated, an operator visually inspects their alignment under a microscope to determine if they are properly aligned. If any portion of the small square lies outside of the large square, then the alignment of the masks exceeds the allowable tolerance.
One problem however with such an optical determination of mask alignment is that it is very time consuming. Visual inspection must be done by the operator for each chip on a wafer; and typically, there are at least 50 chips per wafer. Another problem with the optical inspection method of measuring mask misalignment is that it is subject to human errors due to fatigue and poor judgment by the operator. Further, these problems become more severe as the allowable misalignment goes down.
Accordingly, a primary object of the invention is to provide an improved circuit for measuring the misalignment of the masks which define different conductive layers in an integrated circuit.
Another object of the invention is to provide a circuit which generates electrical signals that digitally indicate the amount of misalignment between conductors that were defined by two different masks.